1. Field of the Invention
The present invention relates to computer systems and, more specifically, to a computer system in which a root device communicates with a plurality of other devices.
2. Description of the Prior Art
In computer systems, increasing processor performance is driving the need for higher bandwidth on input-output (I/O) interfaces, memory interfaces and inter-processor interconnects. Generally, these interfaces are changing from multi-drop bidirectional parallel busses to point-to-point high speed unidirectional serial busses. The higher frequencies required to support the faster data rates can not be supported on multi-drop busses, driving topologies to point-to-point busses.
The directional turn-around penalties on high speed busses with multiple transfers in flight tend to be too extreme, resulting in a transition from shared bidirectional busses to separate unidirectional busses. The power and area expense of the electrical I/O used to drive each unidirectional high speed bus interconnect wire has driven the transition from wide parallel busses to narrow serial busses. On a wide parallel bus, a transaction can be sent in one bus clock cycle across the interface. On a serial bus, the transaction is broken into packets and driven on the bus over multiple clock cycles. The packets are reassembled at the receiving end to form the original transaction.
As serial high speed unidirectional busses become more common in computer systems, techniques must be developed to make them more efficient and reliable. Also, when serial high speed unidirectional busses develop faults or are temporarily congested, data transfer rates can be impacted.
Therefore, there is a need for a high speed unidirectional interconnect that provides both higher reliability and higher efficiency than existing topologies